The present invention relates to a static type random access memory device (SRAM), more particularly to a SRAM having a reset controller for resetting stored data at a high speed.
A conventional memory cell of a static type memory device has a pair of cross coupled transistors, that is, a gate electrode of each transistor being connected to a drain electrode of the other. The gate electrodes are connected to bit lines via transfer gate transistors, respectively. One of the bit lines is used for read access operation and the other is for write access or reset operation, as described below.
A functional block diagram of a static random access memory device is shown in FIG. 6 which has a one mega bits capacity with a bit construction such as 1 mega words.times.1 bit. Memory cells 30 in a cell array are arranged in 1024 rows and 1024 columns, for example. Each of memory cells 30 is placed at a cross section of a word line W1, W2 or Wn and a bit line B0, B1 or Bm, as shown in FIG. 6, wherein only one of each pair of bit lines is shown for simplicity.
In read mode operation, address signals A10-A19 are input to a word decoder 42 through an address bus 41. The decoder 42 decodes the address signals and therefore drives selected one of the word lines Wn to be its active level. Each memory cell 30 corresponding to the word line Wn is connected and outputs its holding data to a respective pair of bit lines. A column selector, which is supplied with address signals A0-A9 via an address bus 41, selects one of the pairs of bit lines and connects it to an input and output terminal 43.
In write mode operation, the decoder 42 decodes the address signals A10-A19 and drives selected one of the word lines Wn. Each memory cell 30 corresponding to the word line Wn is connected to the respective pair of bit lines. The column selector supplied with the address signals A0-A9 selects and drives one of the pairs of bit lines according to an input data from the input and output terminal 43.
A typical circuit configuration of the memory cell 30 so called four transistor type is shown in FIG. 7. Transistors 1 through 4 are of N channel type with back gate electrodes connected to a grounding voltage GND. Drain electrodes of the transistors 1 and 2 are connected to a power supply voltage VDD via load resistances 5 and 6 respectively. Source electrodes of the transistors 1 and 2 are commonly connected to the grounding voltage. Gate electrodes of the transistors 1 and 2 are connected to the drain electrodes of the transistors 2 and 1, respectively. The drain electrodes of the transistors 1 and 2 are also connected to source electrodes of transfer gate transistors 3 and 4 respectively. The gate electrodes of the transfer gate transistors 3 and 4 are commonly connected to a word line Wn. The drain electrodes of the transistors 3 and 4 are connected to bit lines Bm and *Bm respectively. In this case, those two signals one of which is labeled with an asterisk and another of which is not form a complementary pair of signals.
In detail, although only one of the bit lines is shown for each memory cell in FIG. 6, one of the bit lines Bm and *Bm is used for transferring read data and another is used for transferring write data or reset data signal. For example, the bit line *Bm transfers a write data to the memory cell 30 and the bit line Bm transfers a read data from the memory cell. That is, in a write mode operation wherein a data "0" is to be written in the memory cell 30, the bit line *Bm is maintained at a low level by the column selector 43 when the word line Wn in driven to the active level. The transistor 3, with its gate electrode being driven by the word line Wn, turns conductive to transfer the low level of the bit line *Bm to the drain electrode of the transistor 1 and the gate electrode of the transistor 2. The transistor 2 turns nonconductive to raise its drain voltage to the power supply voltage VDD. Then, the transistor 1 turns conductive to maintain the low voltage at the drain electrode thereof. Therefore, even after the word line Wn turns back to its nonactive level, the drain voltage of the transistor 1, which represents a stored data, is maintained stably. In case where a data "1" is to be written in the memory cell 30, the write operation is performed in nearly the same and well known manner. In a read mode operation, after the word line Wn is driven to the active level and the stored data in the memory cell 30 is transferred to the bit lines Bm and *Bm, the column selector 43 selects the bit line Bm and connects it to the input and output terminal 44. The read data signal from the bit line Bm is transferred via the terminal 43 to a read data amplifier (not shown).
In case where a static random access memory device is to be initialized, that is, when the memory cells are to be reset to hold a certain data uniformly, the write operation for writing the certain reset data in the memory cells have to be performed repeatedly. For example, as for a SRAM device of which a write cycle time is 15 ns and a bit construction is 1 mega words.times.1 bit, the reset operation to reset all the memory cells 30 requires a period such as 15.times.10.sup.-9 s.times.2.sup.20 =15728640.times.10.sup.-9 s.apprxeq.16 ms. When the SRAM is connected via a data bus to a microprocessor, the SRAM is initialized in the control of the microprocessor and programs executed therein, causing a long time for reset operation.
A typical example of such a initialization procedure for resetting memory data of a SRAM with a microprocessor is shown in FIG. 8. At first, in a step S1, a base address of the SRAM which is used by the microprocessor for accessing it is set up. A loop counter for control the loop cycles of the procedure is also set up in a step 2. For example, when the initialization is to be performed on all the memory cells, the loop counter is set at 2.sup.20. After that, in a step 3, the write operation is performed to write a initial data, for example "0", in a memory cell indicated by the base address. Then the address is increased in a step S4 and the loop counter is decreased in a step S5. In a step S6, a value of the loop counter is checked and, if the value is "0", the initialization procedure is over. If the value is still larger than "0", the microprocessor gets back to the step S3 and continues to perform the write operation to write the initial data. On the condition that the microprocessor requires, for example, 40 ns for executing each instruction which corresponds each of the steps S1 to S6, the microprocessor requires for performing the initialization procedure a period such as: EQU {1+1+(1+1+1).times.2.sup.20) (steps).times.40.times.10.sup.-9 (seconds).apprxeq.126 ms.
The initial data to be written in the memory cells in the reset operation is common to all the memory cells as mentioned above. However, the reset data is capable of being set for each of the memory cells by programs for the microprocessor. In such a case, the microprocessor generates the reset data patterns according to a increment of the address of the SRAM and writes the respective reset data in a memory cell in each of the write steps S3. For example, in case where the SRAM is used as a cache memory of the microprocessor, the address of the SRAM is used as a cache line address and linked with cache data which represents respective I/O data to be stored in the cache memory, a cache tag which holds an address of the cache data in a main memory, and a cache valid bit which represents whether the cache data is valid or not. In order to perform the initialization operation on such a cache memory, all the valid bits are to be reset to be "0". In addition, a cache system usually performs a certain operation so called cache invalidate operation in which the cache bits are set to be "0" independently from the initialization operation as mentioned above.
Therefore, in the conventional memory device, since the initialization operation is performed by write operation transferring reset data via a data bus to the memory cell, the initialization operation requires a long time period to be performed. In particular, in a SRAM used as a cache memory, the initialization operation or the invalidate operation is required to be performed in a very short time so as to reduce the waiting time of the microprocessor. However, in the conventional device, the initialization operation, which takes about 126 ms as mentioned above, prevent a operation of the microprocessor and decrease total operation speed of the whole data processing system.
There has been proposed an certain type of SRAM device which is capable of performing the reset operations on a plurality of memory cells at a same time. A block diagram of such a device is shown in FIG. 9. The device shown in FIG. 9 is equipped with OR gates each having an output terminal coupled to each of the word lines Wn and one input terminal coupled to the word decoder 42. Another input terminals of each of the OR gates are connected commonly to a inverter 45 for transferring a initialization control signal *INIT when a initialization operation mode. The bit lines Bm, which is used for transferring write or reset data signals, is coupled to the grounding line GND via transfer gate transistors 47 having gate electrode connected to the output of the inverter 45. During the initialization operation mode, the control signal *INIT turns to its active low level. Therefore the inverter 45 supplies a high level signal to all the OR gates, which drive all the word lines Wn to the active high level. At the same time, the bit lines Bm turn to the grounding level. Therefore, all the memory cells in the device is reset at the same time. However, in this device, since the logical OR gates 46 are coupled between the word decoder 42 and the word lines Wn, a operation speed in a usual read or write operation wherein the control signal *INIT is at a high level is decreased by a transfer delay time of those logical OR gates 46. The delay time caused by the gates 46 is, for example, about 3 ns, increasing the total access time in such usual operations from the 15 ns as mentioned above to 18 ns. Moreover, in this device, the reset data are set only for each bit line, that is, the reset data cannot be set for each memory cell independently.